1. Technical Field
This invention relates to data transfer circuits in memory devices or the like, and more particularly to a two-stage bit switch for transferring data between bit lines in a memory device to data lines for output in a read operation.
2. Description of the Related Art
In a memory device of the type having an array of a large number of memory cells on a semiconductor chip, a read operation employs a pair of true and complement bit lines for a column of cells in the array, wherein the data on these bit lines is sensed and transferred to output circuitry. One of the ways to achieve high performance in these memory devices is to speed up this transfer of data in a read operation.
In some prior circuits used in transferring data from bit lines to output circuitry in a read operation, a direct connection between the bit lines and read data lines created a charge sharing problem, whereby data may possibly be read incorrectly. Thus, in order to avoid this charge sharing issue, it is preferred to couple the data on the bit lines to read data output circuitry by a path that does not permit direct currents to flow between the bit lines and the read data lines.
In prior arrangements for read data operations in memory circuits of this type, optimum speed is not achieved because of the time needed in a read operation to transfer data from the bit lines to the read data lines, a problem resulting in part from the delay needed to allow the bit lines to separate or develop a voltage differential large enough for unequivocal sensing in downstream circuitry in the read arrangement. Thus, it is preferable to enable sensing at an earlier point in the cycle of the read operation than has previously been allowed.